1. Field of the Invention
The invention relates to a display control apparatus and, more particularly, to a display control apparatus for forming a frequency that is integer times as high as a frequency of a certain reference signal and performing a display control.
2. Related Background Art
Hitherto, to form a frequency that is integer times as high as a frequency of a certain reference signal from such a reference frequency, a PLL (Phase Locked Loop) as an AFC (Automatic Frequency Control) loop for tracing the frequency of the reference signal and an APC (Automatic Phase Control) loop for tracing the phase of the reference signal is used. Generally, the PLL is constructed by a phase difference detector, a low pass filter (LPF), and a voltage controlled oscillator (VCO). The PLL used here further has a frequency divider.
Ordinarily, a VCO output signal is frequency divided by a predetermined frequency division parameter, a phase of the frequency division result and a phase of the reference signal are compared, and a fluctuation of the reference signal is traced, thereby forming a stable integer-times frequency that is phase locked with the reference signal.
By using such a PLL function, a horizontal sync signal is set to a reference signal to the PLL, thereby reproducing dot clocks of an input video signal source.
When different frequencies exist in a portion or a plurality of portions in the horizontal sync signal, however, since there is one (constant) frequency division parameter, it is impossible to trace the horizontal sync signal and there is a drawback such that the dot clocks are reproduced at an unstable frequency and an unstable phase lock (large jitter).
It is an object of the invention to provide a display control apparatus for reproducing stable dot clocks by phase locking a PLL even when a plurality of frequencies exist in a reference signal.